The present invention relates to a semiconductor memory device in which a pair of bit lines are precharged prior to a read or write operation.
As is well known, a semiconductor memory is structured in that a plurality of memory cells are provided in rows and columns, and word lines and bit line pairs are arranged in rows and columns, respectively. Each of the bit line pairs is composed of a pair of bit lines, and each of the pair of bit lines are equally precharged to a predetermined potential prior to a read or write operation. This precharge of bit lines is conducted by providing precharge transistors between bit lines and a voltage source of the predetermined potential and rendering the precharge transistors conductive.
However, accompanied by the increase in memory capacity, the number of bit lines pairs has been remarkably increased, and this increase in memory capacity has also caused the increase in the number of the precharge transistors for precharging bit lines in each bit line pair. The precharge transistors are simultaneously rendered conductive by a precharge control signal commonly applied to gates of the precharge transistors. Therefore, effective capacitance of the gates of the precharge transistors has inevitably become large. In other words, a load capacitance of the precharge control signal has become large. Accordingly, it has been difficult to drive the precharge transistors at a high speed in response to the precharge control signal and therefore, a time period required to complete the precharge has become large, resulting in low speed operation of memories.